TIER IV Joins Japan’s R&D Program to Open-Source AI Chips for Driving

The initiative, which includes a research team led by Professor Yoshihiro Kawahara of the University of Tokyo, focuses on creating functionally differentiated AI chips. While standard high-performance computing has driven AI progress, it often fails to meet the strict power and real-time constraints required for autonomous vehicles. TIER IV intends to bridge this gap by designing hardware that integrates directly with Autoware, its open-source autonomous driving software.

Central to this architecture is the use of the Tensor Operator Set Architecture (TOSA). By implementing TOSA as an intermediate layer between AI models and hardware, TIER IV allows for software-defined optimization. This approach ensures that as AI models evolve—such as the large-scale Transformer models used for perception and planning—the hardware can adapt through compiler updates rather than requiring costly physical redesigns. The strategy prioritizes performance per watt, aiming to support systems ranging from low-power embedded devices to robust in-vehicle control units.

Transparency and verifiability serve as the final pillars of the project. By making logic designs and toolchains public, TIER IV provides developers and manufacturers with the ability to inspect internal processing flows. Furthermore, the inclusion of formal verification techniques allows for mathematical confirmation that computational transformations, such as quantization, do not compromise the safety or accuracy of the AI’s decision-making process. This shift toward an open-source hardware philosophy seeks to democratize semiconductor development for the next generation of intelligent mobility.